The conventional transistor package structure is classified to three types. The first type is shown as FIG. 1. It is so-called Turbo CSP, and its configuration comprises the first adhesion layer 11, metal layer 12, the second adhesion layer 13, and lead frame 14 in order in the electrical contact surface of the chip 10. The electrical contact and the metal layer 12 of the chip 10 form the electrical connection with the lead frame 14 respectively b employing multiple metal wires 15 to be the main structure characteristic. The transistor comprising this kind of structure characteristic usually includes the drawbacks of slow transportation sped and high defect rate of the package, because the metal wires 15 connecting the chip 10, metal layer 12, and the lead frame 14 are too long and they are point-to-point connections.
The second type of the transistor package structure is shown as FIG. 2, which is so-called Window BGA and its configuration comprises the adherent layer 21, metal layer 22, and solder 23 in order on the electrical contact surface of the chip 20, and employs the metal wires 24 to electrically connect the chip 20, and metal layer 22. But because the kind of transistor package structure only comprises single metal layer 22, signal wire layer and the ground power layer needed by the transistor are both configured in the metal layer 22 in the manufacture procedure. When manufacturing memory with big capacity and numerous wires, the space between wires becomes very tight so that the drawback that the electromagnetic wave interference cannot be reduced happens. And the mental wires 24 electrically connects the chip 20 and the metal layer 22 are too long and the structure is in the manner of point-to-point can also cause the drawbacks of the very slow transportation speed and very high defect rate of the package.
The third type of the transistor package structure is shown in FIG. 3, which is so-called T2BGA. Its difference from the Window BGA is that the T2BGA comprises two metal layers 31 to separate the signal wire layer and the ground power layer for configuration. It performs the better effect of electromagnetic interference compared with the Window BGA. But the T2BGA also needs the metal wires 32 electrical connects the chip 20 and the two metal layer 31. The structure mentioned above can also cause the drawbacks of the very slow transportation speed and very high defect rate of the package.
Therefore, in order to resolve the drawbacks of the several transistors package structure mentioned above, the inventor of the present invention develops a dielectric material layer connected to the electric conducting object and a bump. In the manner of big-area electrical connection by the contact of the surfaces, the dielectric material electrical connected to the first metal layer can accomplish the improvement of the chip package structure which performs the better insulation of the electric noise, the better effect for reducing the electromagnetic interference, the higher transportation speed, and higher yield of the package.